/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Pfu_IpRegs.h                                                                              *
 *  \brief    This file contains interface header for PFU low level driver                              *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2024/11/18     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/
#ifndef PFU_IPREGS_H
#define PFU_IPREGS_H

#define PFU_MODE_CTRL_OFF  0x0U

#define BM_PFU_MODE_CTRL_MODE_SWITCH_DONE  ((uint32_t)0x01U << 31U)

#define BM_PFU_MODE_CTRL_BYPASS_MODE  ((uint32_t)0x01U << 1U)

#define BM_PFU_MODE_CTRL_SW_RST  ((uint32_t)0x01U << 0U)

#define PFU_AXI_SLV_CTRL_OFF  0x4U

#define BM_PFU_AXI_SLV_CTRL_TIMEOUT_EN  ((uint32_t)0x01U << 2U)

#define BM_PFU_AXI_SLV_CTRL_IDLE_STATE  ((uint32_t)0x01U << 1U)

#define BM_PFU_AXI_SLV_CTRL_FLOW_CTRL  ((uint32_t)0x01U << 0U)

#define PFU_AXI_SLV_TIMEOUT_OFF  0x8U

#define FM_PFU_AXI_SLV_TIMEOUT_THRESHOLD  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_AXI_SLV_TIMEOUT_THRESHOLD(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_AXI_SLV_TIMEOUT_THRESHOLD)
#define GFV_PFU_AXI_SLV_TIMEOUT_THRESHOLD(v) \
  (((uint32_t)(v) & FM_PFU_AXI_SLV_TIMEOUT_THRESHOLD) >> 0U)

#define PFU_RBUF_CTRL_OFF  0xcU

#define BM_PFU_RBUF_CTRL_PREF_EN  ((uint32_t)0x01U << 1U)

#define BM_PFU_RBUF_CTRL_RBUF_FLUSH  ((uint32_t)0x01U << 0U)

#define PFU_PREF_REGION_ALIGNMENT(v) ((v) >> 12UL)
#define PFU_PREF_REGION_START_OFF(v)  (0x10U + ((v) * 0x08UL))
#define PFU_PREF_REGION_END_OFF(v)  (0x14U + ((v) * 0x08UL))

#define PFU_PREF_REGION0_START_OFF  0x10U

#define FM_PFU_PREF_REGION0_START_ADDRESS  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_PREF_REGION0_START_ADDRESS(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_PREF_REGION0_START_ADDRESS)
#define GFV_PFU_PREF_REGION0_START_ADDRESS(v) \
  (((uint32_t)(v) & FM_PFU_PREF_REGION0_START_ADDRESS) >> 0U)

#define PFU_PREF_REGION0_END_OFF  0x14U

#define FM_PFU_PREF_REGION0_END_ADDRESS  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_PREF_REGION0_END_ADDRESS(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_PREF_REGION0_END_ADDRESS)
#define GFV_PFU_PREF_REGION0_END_ADDRESS(v) \
  (((uint32_t)(v) & FM_PFU_PREF_REGION0_END_ADDRESS) >> 0U)

#define PFU_PREF_REGION1_START_OFF  0x18U

#define FM_PFU_PREF_REGION1_START_ADDRESS  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_PREF_REGION1_START_ADDRESS(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_PREF_REGION1_START_ADDRESS)
#define GFV_PFU_PREF_REGION1_START_ADDRESS(v) \
  (((uint32_t)(v) & FM_PFU_PREF_REGION1_START_ADDRESS) >> 0U)

#define PFU_PREF_REGION1_END_OFF  0x1cU

#define FM_PFU_PREF_REGION1_END_ADDRESS  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_PREF_REGION1_END_ADDRESS(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_PREF_REGION1_END_ADDRESS)
#define GFV_PFU_PREF_REGION1_END_ADDRESS(v) \
  (((uint32_t)(v) & FM_PFU_PREF_REGION1_END_ADDRESS) >> 0U)

#define PFU_AXI_MST_CTRL_OFF  0x20U

#define BM_PFU_AXI_MST_CTRL_TIMEOUT_EN  ((uint32_t)0x01U << 0U)

#define PFU_AXI_MST_TIMEOUT_OFF  0x24U

#define FM_PFU_AXI_MST_TIMEOUT_THRESHOLD  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_AXI_MST_TIMEOUT_THRESHOLD(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_AXI_MST_TIMEOUT_THRESHOLD)
#define GFV_PFU_AXI_MST_TIMEOUT_THRESHOLD(v) \
  (((uint32_t)(v) & FM_PFU_AXI_MST_TIMEOUT_THRESHOLD) >> 0U)

#define PFU_INT_STAT_OFF  0x30U

#define BM_PFU_INT_STAT_SRAM_RDATA_UNC_ERR  ((uint32_t)0x01U << 4U)

#define BM_PFU_INT_STAT_SRAM_RDATA_COR_ERR  ((uint32_t)0x01U << 3U)

#define BM_PFU_INT_STAT_RESP_ERROR  ((uint32_t)0x01U << 2U)

#define BM_PFU_INT_STAT_AXI_MST_TIMEOUT  ((uint32_t)0x01U << 1U)

#define BM_PFU_INT_STAT_AXI_SLV_TIMEOUT  ((uint32_t)0x01U << 0U)

#define PFU_INT_STAT_EN_OFF  0x34U

#define BM_PFU_INT_STAT_EN_SRAM_RDATA_UNC_ERR  ((uint32_t)0x01U << 4U)

#define BM_PFU_INT_STAT_EN_SRAM_RDATA_COR_ERR  ((uint32_t)0x01U << 3U)

#define BM_PFU_INT_STAT_EN_RESP_ERROR  ((uint32_t)0x01U << 2U)

#define BM_PFU_INT_STAT_EN_AXI_MST_TIMEOUT  ((uint32_t)0x01U << 1U)

#define BM_PFU_INT_STAT_EN_AXI_SLV_TIMEOUT  ((uint32_t)0x01U << 0U)

#define PFU_INT_SIG_EN_OFF  0x38U

#define BM_PFU_INT_SIG_EN_SRAM_RDATA_UNC_ERR  ((uint32_t)0x01U << 4U)

#define BM_PFU_INT_SIG_EN_SRAM_RDATA_COR_ERR  ((uint32_t)0x01U << 3U)

#define BM_PFU_INT_SIG_EN_RESP_ERROR  ((uint32_t)0x01U << 2U)

#define BM_PFU_INT_SIG_EN_AXI_MST_TIMEOUT  ((uint32_t)0x01U << 1U)

#define BM_PFU_INT_SIG_EN_AXI_SLV_TIMEOUT  ((uint32_t)0x01U << 0U)

#define FUSA_COR_ERR_INT_STAT_OFF  0x40U

#define BM_FUSA_COR_ERR_INT_STAT_MST_RDATA  ((uint32_t)0x01U << 3U)

#define BM_FUSA_COR_ERR_INT_STAT_SLV_ARADDR  ((uint32_t)0x01U << 2U)

#define BM_FUSA_COR_ERR_INT_STAT_SRAM_RDATA_COR_ERR  ((uint32_t)0x01U << 1U)

#define FUSA_COR_ERR_INT_STAT_EN_OFF  0x44U

#define BM_FUSA_COR_ERR_INT_STAT_EN_MST_RDATA  ((uint32_t)0x01U << 3U)

#define BM_FUSA_COR_ERR_INT_STAT_EN_SLV_ARADDR  ((uint32_t)0x01U << 2U)

#define BM_FUSA_COR_ERR_INT_STAT_EN_SRAM_RDATA_COR_ERR  ((uint32_t)0x01U << 1U)

#define FUSA_COR_ERR_INT_SIG_EN_OFF  0x48U

#define BM_FUSA_COR_ERR_INT_SIG_EN_MST_RDATA  ((uint32_t)0x01U << 3U)

#define BM_FUSA_COR_ERR_INT_SIG_EN_SLV_ARADDR  ((uint32_t)0x01U << 2U)

#define BM_FUSA_COR_ERR_INT_SIG_EN_SRAM_RDATA_COR_ERR  ((uint32_t)0x01U << 1U)

#define FUSA_UNCOR_ERR_INT_STAT_OFF  0x50U

#define BM_FUSA_UNCOR_ERR_INT_STAT_SRAM_RDATA_UNC_ERR  ((uint32_t)0x01U << 20U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_MST_REOBI  ((uint32_t)0x01U << 18U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_MST_RVALID  ((uint32_t)0x01U << 17U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_MST_RCTL  ((uint32_t)0x01U << 16U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_MST_RDATA  ((uint32_t)0x01U << 15U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_MST_RID  ((uint32_t)0x01U << 14U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_MST_ARREADY  ((uint32_t)0x01U << 13U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_SLV_ARCTLPTY  ((uint32_t)0x01U << 12U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_SLV_ARUSER  ((uint32_t)0x01U << 11U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_SLV_ARVALID  ((uint32_t)0x01U << 10U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_SLV_ARCTL1  ((uint32_t)0x01U << 9U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_SLV_ARCTL0  ((uint32_t)0x01U << 8U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_SLV_ARADDR  ((uint32_t)0x01U << 7U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_SLV_ARID  ((uint32_t)0x01U << 6U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_SLV_RREADY  ((uint32_t)0x01U << 5U)

#define FUSA_UNCOR_ERR_INT_STAT_EN_OFF  0x54U

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SRAM_RDATA_UNC_ERR  ((uint32_t)0x01U << 20U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_MST_REOBI  ((uint32_t)0x01U << 18U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_MST_RVALID  ((uint32_t)0x01U << 17U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_MST_RCTL  ((uint32_t)0x01U << 16U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_MST_RDATA  ((uint32_t)0x01U << 15U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_MST_RID  ((uint32_t)0x01U << 14U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_MST_ARREADY  ((uint32_t)0x01U << 13U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SLV_ARCTLPTY  ((uint32_t)0x01U << 12U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SLV_ARUSER  ((uint32_t)0x01U << 11U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SLV_ARVALID  ((uint32_t)0x01U << 10U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SLV_ARCTL1  ((uint32_t)0x01U << 9U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SLV_ARCTL0  ((uint32_t)0x01U << 8U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SLV_ARADDR  ((uint32_t)0x01U << 7U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SLV_ARID  ((uint32_t)0x01U << 6U)

#define BM_FUSA_UNCOR_ERR_INT_STAT_EN_SLV_RREADY  ((uint32_t)0x01U << 5U)

#define FUSA_UNCOR_ERR_INT_SIG_EN_OFF  0x58U

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SRAM_RDATA_UNC_ERR  ((uint32_t)0x01U << 20U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_MST_REOBI  ((uint32_t)0x01U << 18U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_MST_RVALID  ((uint32_t)0x01U << 17U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_MST_RCTL  ((uint32_t)0x01U << 16U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_MST_RDATA  ((uint32_t)0x01U << 15U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_MST_RID  ((uint32_t)0x01U << 14U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_MST_ARREADY  ((uint32_t)0x01U << 13U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SLV_ARCTLPTY  ((uint32_t)0x01U << 12U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SLV_ARUSER  ((uint32_t)0x01U << 11U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SLV_ARVALID  ((uint32_t)0x01U << 10U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SLV_ARCTL1  ((uint32_t)0x01U << 9U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SLV_ARCTL0  ((uint32_t)0x01U << 8U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SLV_ARADDR  ((uint32_t)0x01U << 7U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SLV_ARID  ((uint32_t)0x01U << 6U)

#define BM_FUSA_UNCOR_ERR_INT_SIG_EN_SLV_RREADY  ((uint32_t)0x01U << 5U)

#define ERR_INJ_EN_OFF  0x60U

#define BM_ERR_INJ_EN_IRQ  ((uint32_t)0x01U << 6U)

#define FM_ERR_INJ_EN_SRAM_RD_DATA  ((uint32_t)0x3U << 4U)
#define FV_ERR_INJ_EN_SRAM_RD_DATA(v) \
  (((uint32_t)(v) << 4U) & FM_ERR_INJ_EN_SRAM_RD_DATA)
#define GFV_ERR_INJ_EN_SRAM_RD_DATA(v) \
  (((uint32_t)(v) & FM_ERR_INJ_EN_SRAM_RD_DATA) >> 4U)

#define FM_ERR_INJ_EN_AXI_MST_RDATA  ((uint32_t)0x3U << 2U)
#define FV_ERR_INJ_EN_AXI_MST_RDATA(v) \
  (((uint32_t)(v) << 2U) & FM_ERR_INJ_EN_AXI_MST_RDATA)
#define GFV_ERR_INJ_EN_AXI_MST_RDATA(v) \
  (((uint32_t)(v) & FM_ERR_INJ_EN_AXI_MST_RDATA) >> 2U)

#define BM_ERR_INJ_EN_AXI_SLV_ARADDR  ((uint32_t)0x01U << 1U)

#define BM_ERR_INJ_EN_APB_PWDATA  ((uint32_t)0x01U << 0U)

#define ERR_INJ_DATA_HIGH_OFF  0x64U

#define FM_ERR_INJ_DATA_HIGH_HIGH_BITS  ((uint32_t)0xffffffffU << 0U)
#define FV_ERR_INJ_DATA_HIGH_HIGH_BITS(v) \
  (((uint32_t)(v) << 0U) & FM_ERR_INJ_DATA_HIGH_HIGH_BITS)
#define GFV_ERR_INJ_DATA_HIGH_HIGH_BITS(v) \
  (((uint32_t)(v) & FM_ERR_INJ_DATA_HIGH_HIGH_BITS) >> 0U)

#define ERR_INJ_DATA_LOW_OFF  0x68U

#define FM_ERR_INJ_DATA_LOW_LOW_BITS  ((uint32_t)0xffffffffU << 0U)
#define FV_ERR_INJ_DATA_LOW_LOW_BITS(v) \
  (((uint32_t)(v) << 0U) & FM_ERR_INJ_DATA_LOW_LOW_BITS)
#define GFV_ERR_INJ_DATA_LOW_LOW_BITS(v) \
  (((uint32_t)(v) & FM_ERR_INJ_DATA_LOW_LOW_BITS) >> 0U)

#define ERR_INJ_ECC_OFF  0x6cU

#define FM_ERR_INJ_ECC_BITS  ((uint32_t)0xffffffffU << 0U)
#define FV_ERR_INJ_ECC_BITS(v) \
  (((uint32_t)(v) << 0U) & FM_ERR_INJ_ECC_BITS)
#define GFV_ERR_INJ_ECC_BITS(v) \
  (((uint32_t)(v) & FM_ERR_INJ_ECC_BITS) >> 0U)

#define LSP_ERR_STAT_OFF  0x70U

#define BM_LSP_ERR_STAT_BYPASS_MODE_ERR  ((uint32_t)0x01U << 5U)

#define BM_LSP_ERR_STAT_IRQ  ((uint32_t)0x01U << 4U)

#define BM_LSP_ERR_STAT_SRAM_CTRL  ((uint32_t)0x01U << 3U)

#define BM_LSP_ERR_STAT_AXI_MST  ((uint32_t)0x01U << 2U)

#define BM_LSP_ERR_STAT_AXI_SLV  ((uint32_t)0x01U << 1U)

#define BM_LSP_ERR_STAT_APB  ((uint32_t)0x01U << 0U)

#define LSP_ERR_STAT_EN_OFF  0x74U

#define BM_LSP_ERR_STAT_EN_BYPASS_MODE_ERR  ((uint32_t)0x01U << 5U)

#define BM_LSP_ERR_STAT_EN_IRQ  ((uint32_t)0x01U << 4U)

#define BM_LSP_ERR_STAT_EN_SRAM_CTRL  ((uint32_t)0x01U << 3U)

#define BM_LSP_ERR_STAT_EN_AXI_MST  ((uint32_t)0x01U << 2U)

#define BM_LSP_ERR_STAT_EN_AXI_SLV  ((uint32_t)0x01U << 1U)

#define BM_LSP_ERR_STAT_EN_APB  ((uint32_t)0x01U << 0U)

#define LSP_ERR_SIG_EN_OFF  0x78U

#define BM_LSP_ERR_SIG_EN_BYPASS_MODE_ERR  ((uint32_t)0x01U << 5U)

#define BM_LSP_ERR_SIG_EN_IRQ  ((uint32_t)0x01U << 4U)

#define BM_LSP_ERR_SIG_EN_SRAM_CTRL  ((uint32_t)0x01U << 3U)

#define BM_LSP_ERR_SIG_EN_AXI_MST  ((uint32_t)0x01U << 2U)

#define BM_LSP_ERR_SIG_EN_AXI_SLV  ((uint32_t)0x01U << 1U)

#define BM_LSP_ERR_SIG_EN_APB  ((uint32_t)0x01U << 0U)

#define LSP_ERR_INJ_EN_OFF  0x80U

#define BM_LSP_ERR_INJ_EN_IRQ  ((uint32_t)0x01U << 4U)

#define BM_LSP_ERR_INJ_EN_SRAM_CTRL  ((uint32_t)0x01U << 3U)

#define BM_LSP_ERR_INJ_EN_AXI_MST  ((uint32_t)0x01U << 2U)

#define BM_LSP_ERR_INJ_EN_AXI_SLV  ((uint32_t)0x01U << 1U)

#define BM_LSP_ERR_INJ_EN_APB  ((uint32_t)0x01U << 0U)

#define LSP_ERR_INJ_BITS_OFF  0x84U

#define FM_LSP_ERR_INJ_BITS_BIT  ((uint32_t)0xffU << 0U)
#define FV_LSP_ERR_INJ_BITS_BIT(v) \
  (((uint32_t)(v) << 0U) & FM_LSP_ERR_INJ_BITS_BIT)
#define GFV_LSP_ERR_INJ_BITS_BIT(v) \
  (((uint32_t)(v) & FM_LSP_ERR_INJ_BITS_BIT) >> 0U)

#define PFU_SELF_TEST_OFF  0x90U

#define BM_PFU_SELF_TEST_EN  ((uint32_t)0x01U << 0U)

#define PFU_UNC_INT_STAT_OFF  0xa0U

#define BM_PFU_UNC_INT_STAT_RESP_ERROR  ((uint32_t)0x01U << 2U)

#define BM_PFU_UNC_INT_STAT_AXI_MST_TIMEOUT  ((uint32_t)0x01U << 1U)

#define BM_PFU_UNC_INT_STAT_AXI_SLV_TIMEOUT  ((uint32_t)0x01U << 0U)

#define PFU_UNC_INT_STAT_EN_OFF  0xa4U

#define BM_PFU_UNC_INT_STAT_EN_RESP_ERROR  ((uint32_t)0x01U << 2U)

#define BM_PFU_UNC_INT_STAT_EN_AXI_MST_TIMEOUT  ((uint32_t)0x01U << 1U)

#define BM_PFU_UNC_INT_STAT_EN_AXI_SLV_TIMEOUT  ((uint32_t)0x01U << 0U)

#define PFU_UNC_INT_SIG_EN_OFF  0xa8U

#define BM_PFU_UNC_INT_SIG_EN_RESP_ERROR  ((uint32_t)0x01U << 2U)

#define BM_PFU_UNC_INT_SIG_EN_AXI_MST_TIMEOUT  ((uint32_t)0x01U << 1U)

#define BM_PFU_UNC_INT_SIG_EN_AXI_SLV_TIMEOUT  ((uint32_t)0x01U << 0U)

#define PFU_DEBUG0_OFF  0x100U

#define FM_PFU_DEBUG0_SLV_REC_NUM  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_DEBUG0_SLV_REC_NUM(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_DEBUG0_SLV_REC_NUM)
#define GFV_PFU_DEBUG0_SLV_REC_NUM(v) \
  (((uint32_t)(v) & FM_PFU_DEBUG0_SLV_REC_NUM) >> 0U)

#define PFU_DEBUG1_OFF  0x104U

#define FM_PFU_DEBUG1_SLV_SEND_NUM  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_DEBUG1_SLV_SEND_NUM(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_DEBUG1_SLV_SEND_NUM)
#define GFV_PFU_DEBUG1_SLV_SEND_NUM(v) \
  (((uint32_t)(v) & FM_PFU_DEBUG1_SLV_SEND_NUM) >> 0U)

#define PFU_DEBUG2_OFF  0x108U

#define FM_PFU_DEBUG2_MST_SEND_NUM  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_DEBUG2_MST_SEND_NUM(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_DEBUG2_MST_SEND_NUM)
#define GFV_PFU_DEBUG2_MST_SEND_NUM(v) \
  (((uint32_t)(v) & FM_PFU_DEBUG2_MST_SEND_NUM) >> 0U)

#define PFU_DEBUG3_OFF  0x10cU

#define FM_PFU_DEBUG3_MST_REC_NUM  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_DEBUG3_MST_REC_NUM(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_DEBUG3_MST_REC_NUM)
#define GFV_PFU_DEBUG3_MST_REC_NUM(v) \
  (((uint32_t)(v) & FM_PFU_DEBUG3_MST_REC_NUM) >> 0U)

#define PFU_DEBUG_CTRL_OFF  0x120U

#define BM_PFU_DEBUG_CTRL_LOCK  ((uint32_t)0x01U << 1U)

#define BM_PFU_DEBUG_CTRL_CLEAR  ((uint32_t)0x01U << 0U)

#define PFU_RBUF_HIT_CNT_OFF  0x130U

#define FM_PFU_RBUF_HIT_CNT_CNT  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_RBUF_HIT_CNT_CNT(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_RBUF_HIT_CNT_CNT)
#define GFV_PFU_RBUF_HIT_CNT_CNT(v) \
  (((uint32_t)(v) & FM_PFU_RBUF_HIT_CNT_CNT) >> 0U)

#define PFU_RBUF_MISS_CNT_OFF  0x134U

#define FM_PFU_RBUF_MISS_CNT_CNT  ((uint32_t)0xffffffffU << 0U)
#define FV_PFU_RBUF_MISS_CNT_CNT(v) \
  (((uint32_t)(v) << 0U) & FM_PFU_RBUF_MISS_CNT_CNT)
#define GFV_PFU_RBUF_MISS_CNT_CNT(v) \
  (((uint32_t)(v) & FM_PFU_RBUF_MISS_CNT_CNT) >> 0U)

#define REVISION_OFF  0xfff0U

#endif /* PFU_IPREGS_H */
/* End of file */
